Modified Booth Multiplier with Carry Select Adder using 3-stage Pipelining Technique
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چکیده
This paper presents a high-speed and low area 16 ×16 bit Modified Booth Multiplier (MBM) by using Carry Select Adder (CSA) and 3-stage pipelining technique. CSA improves the performance of MBM and pipelining technique reduces the delay time. Using these techniques, the delay is reduced by 56% and the numbers of SLICES and LUT's are reduced by 4% as compared to high speed MBM. The multiplier circuit is designed using VHDL and simulated using Xilinx ISE Simulator. The power metric of the MBM is evaluated using Cadence tools
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تاریخ انتشار 2012